ADT7468ZEVB【PDF 23/81 页】BOARD EVAL FOR ADT7468

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ADT7468

For applications where the monitoring cycle time is important,

it can be calculated easily.

The measured channels are

Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has

been exceeded.

Bit 5 (LT) = 1, local temperature high or low limit has been

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Four dedicated supply voltage inputs

Supply voltage (V CC pin)

Local temperature

Two remote temperatures

exceeded.

Bit 4 (R1T) = 1, Remote 1 temperature high or low limit has

been exceeded.

Bit 3 (5 V) = 1, 5 V high or low limit has been exceeded.

Bit 2 (V CC ) = 1, V CC high or low limit has been exceeded.

As mentioned previously, the ADC performs round-robin

conversions and takes 11 ms for each voltage measurement,

12 ms for a local temperature reading, and 39 ms for each

remote temperature reading. The total monitoring cycle time

for averaged voltage and temperature monitoring is, therefore,

nominally

(5 × 11) + 12 + (2 × 39) = 145 ms

Fan TACH measurements are made in parallel and are not

synchronized with the analog measurements in any way.

STATUS REGISTERS

The results of limit comparisons are stored in Status Registers 1

and 2. The status register bit for each channel reflects the status

of the last measurement and limit comparison on that channel.

If a measurement is within limits, the corresponding status

register bit is cleared to 0. If the measurement is out-of-limit,

the corresponding status register bit is set to 1.

The state of the various measurement channels can be polled by

reading the status registers over the serial bus. In Bit 7 (OOL) of

Status Register 1 (Reg. 0x41), 1 means that an out-of-limit event

has been flagged in Status Register 2. This means that the user

also needs to read Status Register 2. Alternatively, Pin 10 or

Pin 14 can be configured as an SMBALERT output. This hard

interrupt automatically notifies the system supervisor of an out-

of-limit condition. Reading the status registers clears the appro-

priate status bit as long as the error condition that caused the

interrupt has cleared. Status register bits are sticky. The status

bits are referred to as sticky, because they remain set until read

by software. Whenever a status bit is set, indicating an out-of-

limit condition, it remains set even if the event that caused it

has ceased (until read). The only way to clear the status bit is to

read the status register after the event has ceased. Interrupt

status mask registers (0x74, and 0x75) allow individual inter-

Bit 1 (V CCP ) = 1, V CCP high or low limit has been exceeded.

Bit 0 (2.5 V) = 1, 2.5 V high or low limit has been exceeded.

Status Register 2 (Reg. 0x42)

Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.

Bit 6 (D1) = 1, indicates an open or short on D1+/D1– inputs.

Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum

speed. Alternatively, indicates that the THERM limit has been

exceeded, if the THERM function is used.

Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below minimum

speed.

Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum

speed.

Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below minimum

speed.

Bit 1 (OVT) = 1, indicates a THERM overtemperature limit has

been exceeded.

Bit 0 (12V/VC) = 1, indicates a 12 V high or low limit has been

exceeded. If the VID code change function is used, this bit

indicates a change in VID code on the VID0 to VID5 inputs.

INTERRUPTS

SMBALERT Interrupt Behavior

The ADT7468 can be polled for status, or an SMBALERT

interrupt can be generated for out-of-limit conditions. It is

important to note how the SMBALERT output and status bits

behave when writing interrupt handler software.

HIGH LIMIT

TEMPERATURE

CLEARED ON READ

rupt sources to be masked from causing an SMBALERT. How-

ever, if one of these masked interrupt sources goes out-of-limit,

its associated status bit is set in the interrupt status registers.

Status Register 1 (Reg. 0x41)

Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and

“STICKY”

STATUS BIT

SMBALERT

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

(TEMP BELOW LIMIT)

Status Register 2 should be read.

Rev. 3 | Page 23 of 81 | www.onsemi.com

Figure 28. SMBALERT and Status Bit Behavior

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